Story 1: Intel Details 18A-P — 50% Thermal Conductivity Improvement Via New Contact and Interconnect Films
📰 What happened: Intel published a paper at VLSI 2026 detailing its 18A-P process node, introducing new high-performance and low-power RibbonFET variants with enhanced contacts, a 9% iso-power performance gain, and a 50% improvement in thermal conductivity.
🔬 Thin films take: This 50% thermal conductivity number jumps off the page for anyone who’s spent time on a deposition tool. You don’t get that kind of improvement without fundamentally rethinking your contact and middle-of-line (MOL) film stack. The key enabler is almost certainly a new contact metal or liner — think cobalt or ruthenium replacing traditional tungsten in the contact plug, combined with a thinner, higher-quality TiN or TiAl barrier. GAA nanosheets already run hot because the channel is wrapped on all four sides by gate metal — there’s no bulky substrate to sink heat through the way planar FinFETs did. So Intel’s thermal play is about lowering the interfacial thermal resistance between the source/drain epitaxy and the contact metal. That means tighter process control on the silicide formation (likely TiSi or NiPtSi at these dimensions) and a smoother, cleaner interface with fewer phonon-scattering defects. The 18% power reduction at iso-performance also tells me they’ve optimized the high-k/metal gate stack — probably a thinner HfO2-based dielectric with a new capping layer to reduce gate leakage without sacrificing electrostatic control.
One key claim: Intel’s 50% thermal conductivity improvement on 18A-P points to a complete overhaul of the MOL contact film stack — likely cobalt or ruthenium contacts with optimized silicidation — which cuts interfacial thermal resistance where GAA nanosheets need it most.
Source: Tom’s Hardware — Intel details 18A-P
Story 2: TSMC SoIC Roadmap Scales Hybrid Copper Bonding From 9µm to 4.5µm Pitch by 2029
📰 What happened: TSMC outlined its SoIC 3D stacking roadmap with copper hybrid bonding pitch scaling from 9µm to 6µm (current generation) targeting 4.5µm by 2029, while accelerating TSV availability for A14 to just one year after initial production.
🔬 Thin films take: The hybrid copper bonding pitch — 9µm → 6µm → 4.5µm — is a deposition and CMP problem as much as it is a lithography one. At these dimensions, the Cu-CMP step before bonding determines everything. You need mirror-smooth surfaces with angstrom-level dishing control across the full wafer, because any topography at the bonding interface creates voids that kill the dielectric seal and compromise electromigration lifetime. The dielectric layer — typically SiO₂ deposited by PECVD or PE-ALD — has to be dense enough to form a hermetic bond at sub-400°C temperatures required to protect underlying devices. TSMC’s ability to accelerate A14 TSV availability to just one year after node launch tells me they’ve solved a significant via-middle TSV integration issue — probably a new liner/barrier scheme that can handle the aspect ratios required for A14’s backside power delivery network. The film stress management challenge of stacking two thinned wafers with BSPDN on one side and hybrid bonds on the other is a multi-film stress engineering problem our simulation tools are still catching up to.
One key claim: Scaling SoIC hybrid copper bonding to 4.5µm pitch by 2029 requires sub-angstrom CMP dishing control on the Cu/dielectric interface — a thin films process challenge that is harder than the lithography at these dimensions.
Source: Tom’s Hardware — TSMC SoIC roadmap
Story 3: US Halts Tool Exports to Hua Hong — Deposition and Etch Equipment Supply Chain Impacted
📰 What happened: The US Commerce Department ordered chip equipment companies to halt shipments to Hua Hong Semiconductor and Huali Microelectronics, which are reportedly preparing a 7nm fab in Shanghai. Applied Materials and Lam Research stocks declined on the news.
🔬 Thin films take: This one hits closer to home for anyone working deposition and etch. Hua Hong is primarily a specialty foundry running mature nodes for power management ICs, MCUs, and display drivers — heavy consumers of thick-film deposition processes (TEOS oxides, PSG/BPSG interlayer dielectrics, thick aluminum reflow for power devices). Cutting off tool access for specialty business is one thing, but the real story is the reported 7nm fab ambition. At 7nm, you need ALD high-k/metal gate stacks (HfO₂ with LaO or Al₂O₃ capping layers), advanced spacer films (Si₃N₄, SiBCN), and multi-layer EUV-compatible hardmasks. None of that is available from domestic Chinese tool makers at volume production scale. Naura has made progress on PVD and etch, and AMEC has dielectric etch tools that work, but ALD high-k deposition for a 7nm gate stack? They’re years behind Applied’s Centura and Lam’s Vector platforms. The cost here is measured in yield — every wafer that fails due to film thickness non-uniformity or particle contamination from a less mature tool is a direct hit. For specialty films like stress-engineered SiN liners that drive SRAM performance at advanced nodes, the process window is so tight that even mature tools struggle.
One key claim: China’s domestic tool ecosystem lacks production-capable ALD platforms for 7nm high-k/metal gate stacks — Applied Materials and Lam Research control the film quality and uniformity that 7nm yield depends on.
Source: Tom’s Hardware — US halts exports to Hua Hong; Reuters