Thin Films This Week — May 08, 2026

Thin Films This Week — May 08, 2026

Your weekly Fab Floor Briefing from chipsandchange.tech — three stories from the past week that matter for thin films, deposition, and process engineering.

1. TSMC Overhauls Fab 15A: 28nm → 4nm Means a Complete Thin-Film Tool Chain Swap

What happened: TSMC has begun converting its Fab 15A in Central Taiwan Science Park from legacy 28/22nm production to 4nm-class manufacturing, with NT$100 billion (~$3.1B) in cleanroom and equipment investment. The company’s 1.4nm Taichung site is simultaneously coming together ahead of schedule.

Thin films take:
This isn’t a fab “retooling” — it’s a gut-and-rebuild. I’ve lived through node migrations before, and going from 28nm planar to FinFET-class 4nm (N4/N5 derivative) means every deposition chamber in the line gets swapped. The legacy 28nm line ran thick TEOS SiO₂, conventional SiN, and aluminum pad metallization — workhorse recipes on mature PECVD and PVD hardware. 4nm means cobalt interconnects, area-selective ALD for self-aligned vias, high-aspect-ratio gap-fill with cyclic deposition-etch processes, multi-layer EUV hardmask stacks, and low-k dielectrics that can’t survive a wet clean. That’s a full changeout of PECVD, PE-ALD, thermal ALD, and PVD chambers from every major tool vendor. Fab 15A’s old Applied Materials Producer and Lam Sequel chambers won’t see a single wafer at 4nm. The relocation of that legacy gear to secondary markets (mature-node fabs in China, foundry partners) is its own logistics story. Meanwhile, the 1.4nm Taichung greenfield coming together ahead of schedule suggests the tool install teams are pulling double shifts on both projects. For those of us in process integration, this means six months of intense qualification lots, film stress matching on new chamber hardware, and probably a few dozen OOC events before the deposition recipes converge.

Key claim: Every single thin-film deposition chamber in Fab 15A is being replaced — 4nm uses fundamentally different dielectrics, liners, and metallization than 28nm.

2. NVIDIA and Corning Bet Big on Optical Fiber — Copper Interconnects Face a Materials Challenge

What happened: NVIDIA announced a multi-year partnership with Corning investing an initial $300M (scaling up to $3.2B) to build three new U.S. optical fiber plants, aiming to replace copper cabling in AI rack-scale systems with advanced optical connectivity.

Thin films take:
The copper-vs-optical debate in data center interconnects has been simmering for years, but this deal tells me the inflection point is real. From a thin-films perspective, optical fiber itself is a layered dielectric structure — the cladding and core are doped silica deposited by modified CVD (OVD or VAD processes, not PECVD but chemically analogous). What’s more interesting for our world is the coating stack: each fiber gets dual-layer UV-cured acrylate coatings for mechanical protection, applied on-draw at line speeds exceeding 50 m/s. The film thickness uniformity requirement (±2 µm on a 250 µm coating) is less demanding than wafer processing, but the throughput requirements are staggering. On the transceiver side — and this is where semiconductor thin films come back in — these fibers terminate in silicon photonics or InP PICs that demand precisely controlled dielectric cladding layers (SiO₂, SiN, oxynitride) deposited by PECVD on 300mm wafers, then integrated with copper BEOL stacks. NVIDIA’s bet is that the optical I/O energy-per-bit advantage justifies replacing miles of copper traces in DGX pods. For process engineers, this means more wafers running through photonic-specific PECVD and ALD processes, and growing demand for edge-coupling AR coatings and spot-size converters that require nanometer-precision deposited tapers.

Key claim: Optical fiber is itself a precision thin-film structure (dual-layer UV-cured coatings on doped silica), and the transceiver ecosystem it feeds depends on PECVD-deposited dielectric cladding on 300mm photonic wafers.

3. SK Hynix Hits Zero Available HBM Capacity — The Advanced Packaging Deposition Constraint Bites

What happened: SK Hynix reports effectively zero available HBM3 and DRAM capacity, with customers (NVIDIA, Google, Amazon, Microsoft) offering to co-invest in new fab lines, buy EUV tools, and fund expansion just to secure allocation.

Thin films take:
People see “memory shortage” and think bit density — but anyone who’s spent time in a packaging fab knows the real bottleneck isn’t the front-end transistor. It’s the back-end-of-line and advanced packaging. HBM3E stacks 12 dies vertically, each connected by through-silicon vias (TSVs) that demand conformal SiO₂ liner deposition by PE-ALD at aspect ratios exceeding 20:1, a barrier/seed stack (TiN/Cu by PVD or ALD) with step coverage below 5% on the sidewall, and then bottom-up copper electroplating. Every TSV in every tier of every stack. Then there’s hybrid Cu-Cu bonding — the die-to-die interface requires CMP planarization of the Cu/dielectric surface to <1nm RRMS before plasma activation and room-temperature direct bonding. That’s a surface preparation and surface chemistry problem as much as a deposition one. If SK Hynix’s capacity is truly zero, it means their TSV etch/deposition and hybrid bonding lines are at 100% utilization — and the bottleneck becomes how quickly Lam, AMAT, and TEL can ship and install the next generation of TSV PE-ALD chambers and bonders (SUSS, Applied) into the new M15X and Yongin fabs. The customer offers to buy EUV machines are dramatic, but what they should be offering to fund are TSV dielectric ALD tools and Cu-Cu bonder platforms — the front-end lithography isn’t what’s constraining HBM output; the inter-die connectivity stack is.

Key claim: SK Hynix’s HBM capacity crisis is fundamentally an advanced packaging deposition constraint — TSV dielectric ALD, Cu seed PVD, and hybrid bonding surface preparation are the real gating processes, not front-end lithography.

That’s your Fab Floor Briefing for May 08, 2026. Next week we’ll be watching TSMC’s 1.4nm tool install roadmap, the Corning/NVIDIA fiber coating specs, and whether the SK Hynix customer co-investment model changes how deposition tool capacity is reserved.