Three stories this week, and the through-line is film control at scale. Intel is closing the defect-density gap on 14A faster than any node since 22nm, SK hynix is moving the HBM film stack to Indiana, and Kioxia and SanDisk are betting $31 billion that 3D NAND’s dielectric stack is still the roadmap.
Intel’s 14A Defect Learning Curve Is the Best Since 22nm
What happened: Intel’s CFO said 14A defect density is dropping faster than the company expected, the best learning-curve performance since 22nm, and that foundry customers have shifted from evaluating data to competing for capacity (Tom’s Hardware, Tech Times, Moomoo).
Thin films take: For anyone who has spent a decade chasing defect density on leading-edge logic, that CFO line lands hard: 14A is learning faster than anything since 22nm. I know what that means on the floor. It means high-NA EUV single-exposure patterning is holding up, which removes a whole class of overlay and edge-placement defects, but it also means the films underneath are behaving. The high-k gate stack, the work-function metals, and tens of interconnect levels with their barriers, liners, and CMP steps are each a defect generator that has to be tamed in parallel. When customers stop asking for yield data and start asking for capacity, the process control loop has closed faster than the roadmap allowed, and that is a deposition and polish win as much as a litho one. A node’s defect density is a thin-films and CMP story long before it is a litho story.
SK hynix Breaks Ground on Its First US HBM Base in Indiana
What happened: SK hynix held the groundbreaking for its first US HBM production base in Indiana, a roughly $4 billion packaging-and-test focused campus targeting mass production around 2028 to 2029, with the CEO calling Indiana a key memory base by 2030 (SK hynix, Reuters, TechPowerUp).
Thin films take: Groundbreaking in Indiana is where HBM stops being a memory story and becomes a packaging and films story. HBM is built by stacking, and stacking is film engineering: TSVs etched through thinned die and filled with barrier, seed, and copper, hybrid-bonded oxide surfaces polished flat within nanometers, non-conductive films laminated at temperature, and base dies carrying logic-class BEOL. Every stack-height increase multiplies the grind, the deposition, and the bond steps, and each one is a yield event waiting to happen. Standing this up on US soil means duplicating not just the toolset but the recipe book and the people who carry the process knowledge. That is the real multi-year qualification. The yield of an HBM stack is decided at the bond interface, not in the DRAM cell.
Kioxia and SanDisk Commit $31 Billion to Japan’s 3D NAND Build-Out
What happened: Kioxia and SanDisk plan to invest more than $31 billion in Japan through 2032 for 3D NAND capacity, led by the new Fab 3 at Kioxia’s Kitakami plant, as AI-driven demand tightens NAND supply and the pair looks to close the gap with Samsung and SK hynix (Bloomberg, The Japan Times, StorageReview).
Thin films take: More than $31 billion into 3D NAND says the industry still believes the dielectric stack is the roadmap. For films people, 3D NAND is the most deposition-heavy product in the fab: alternating oxide and nitride layers hundreds deep, each interface a potential trap site, each word line a metal fill into an aspect ratio that keeps getting crueler. The move from tungsten to molybdenum word lines, taller ONON stacks, and keeping the stress balanced so the wafer does not bow, that is where the capital actually lands. Kitakami Fab 3 is really a bet that high-aspect-ratio deposition and etch mature faster than the competition’s. 3D NAND is a thin-film deposition business wearing a memory company’s clothes.
RELATED POSTS
View all
