Friday, Friday, May 29, 2026
Three stories caught my eye this week — each one a reminder that what looks like business news from the outside is, on the fab floor, a thin-films problem waiting to be solved.
1. Samsung Ships World’s First HBM4E 12-Layer Samples — Hybrid Bonding Goes Mainstream
What happened: Samsung Electronics began shipping the industry’s first 12-layer HBM4E samples to global customers on May 29, delivering 16 Gbps per pin (20% faster than HBM4), 48 GB capacity per stack, and 3.6 TB/s bandwidth — pulling ahead of SK Hynix and Micron on the next-generation HBM roadmap.
Thin films take: For those of us who’ve spent years fighting Cu pillar coplanarity on thermal compression bonders, HBM4E at 12 layers means the hybrid bonding transition is no longer theoretical — it’s in customer hands. Moving from microbump to Cu-Cu hybrid bonding at this stack height changes everything about the dielectric deposition flow. You’re no longer trying to keep 25µm solder bumps uniform across a 12-high stack; you’re now controlling a 500nm dielectric CMP process across a bonded interface that has to survive thermal cycling at under 1µm total stack bow. Samsung is running this on 1α-class DRAM, which means the buried bitline and capacitor contacts underneath have their own thermal budget constraints. The dielectric gap-fill for the hybrid bond interface at 12 layers is now the yield-limiting process step — not the DRAM cell itself. I’ve been watching HBM process integration since HBM2, and this is the first generation where the bonding layers dictate more of the final yield than the memory arrays.
2. Intel Signs $3.3B Glass Core Substrate MoU with Odisha, India — A New Thin-Films Manufacturing Frontier
What happened: Intel and 3D Glass Solutions (3DGS) signed a $3.3B MoU with the Government of Odisha on May 29 to build an advanced packaging glass core substrate manufacturing facility near Bhubaneswar — one of India’s largest high-tech manufacturing investments — targeting 1,800+ jobs in a first-of-its-kind Indian project for substrate-level packaging.
Thin films take: Glass core substrates are where the thin-films community gets to reinvent everything we thought we knew about packaging. If you’ve ever dealt with organic substrate warpage on a 100mm×100mm package body, you know why foundries are desperate for a replacement: BT resin and Ajinomoto build-up films just can’t hold flat at the reticle sizes AI accelerators demand. Glass changes the game, but it brings a whole different set of deposition challenges. Getting metal adhesion layers to stick to bare glass at the 2/2µm L/S that advanced packages now require means we have to completely rethink the PVD seed and electroless Cu sequences that have been standard on organic substrates for two decades. 3DGS brings their TGV (through-glass via) expertise, which is a wet-etch + dry-film laminography process that most of the semi world hasn’t touched. I’ll be watching how they handle the dielectric build-up on glass — that interface between the glass carrier and the first redistribution layer is going to define defect density for the whole module.
3. TSMC COUPE Silicon Photonics Begins Volume Production — Foundry-Scale Optical Interconnects Arrive
What happened: TSMC’s COUPE (Compact Universal Photonic Engine) platform is entering volume production in H2 2026, with AMD as the initial adopter, and Nvidia’s Rubin Ultra likely to follow — while Samsung’s rival silicon photonics foundry platform targets 2028 mass production and 2029 CPO turnkey, according to Commercial Times and Ming-Chi Kuo analyses.
Thin films take: Silicon photonics at foundry scale is a thin-films integration problem dressed up as an optics play. COUPE’s first-generation die — the one AMD is taping out now — stacks a photonic IC (PIC) directly on top of an electrical IC (EIC) using TSMC’s own hybrid bonding. That means your standard 300mm fab line is now running SiN waveguide deposition, Ge epitaxy for photodetectors, and oxide cladding layers through tools that used to be reserved for Cu damascene and ILD. The SiN film stress uniformity across a 300mm wafer for a waveguide core that has to maintain ±1nm thickness variation over centimeters of spiral path is tighter than anything most PECVD chamber apps have been asked to deliver. And the edge coupler — where light enters from a fiber — requires a facet etch through multiple dielectric stacks with a sidewall angle tolerance that makes gate spacer etch look like rough carpentry. This is where the thin-films world collides with photonics-grade process control, and the overlap in capability sets is still thin on the ground. If you’re a deposition engineer who hasn’t started thinking about SiN film stress engineering for photonic waveguides, your next performance review may be an uncomfortable one.
— Your Fab Floor Correspondent
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