Thin Films This Week — July 10, 2026

Welcome back to the Fab Floor Briefing. Three stories caught my eye this week: a breakthrough in ALD-grown ferroelectric TiO₂ films that could reshape high-k dielectric stacks, Intel’s dual-sided power delivery play for 14A2 and what it means for the backside metallization workflow, and Applied Materials’ new deposition/etch hardware targeting the DRAM and advanced packaging segments. Let’s get into it.

1. Ferroelectric TiO₂ at the 3nm Limit — ALD Does It Again

What happened: UC Berkeley researchers led by Sayeef Salahuddin demonstrated that titanium dioxide (TiO₂) becomes ferroelectric when deposited thinner than 3nm using atomic layer deposition, with stable polarization down to ~1nm — roughly two unit cells thick. (Source: Semiconductor Engineering, Research Bits — July 6)

Thin films take: I’ve been running ALD chambers since the days when we’d call anything under 10Å a ‘conformal film’ and call it a day. This one hits different. TiO₂ is everywhere in our toolset — it’s the standard high-k dielectric in DRAM capacitors, a common interfacial layer in gate stacks, and we use it in optical coatings without thinking twice. The idea that simply pushing the film below 3nm unlocks a ferroelectric phase — that’s not just a physics curiosity. That’s a potential single-material replacement for the entire FEOL high-k/ferroelectric stack in FeFET and FRAM applications. No more wrestling with HZO/HfO₂ doping ratios, no more worrying about wake-up effects in the first 10⁵ cycles. The team grew these films at sub-400 °C on both crystalline Si and amorphous carbon substrates, which means the ALD process window is already fab-compatible. What I want to see next is cycling endurance data and retention at 85 °C — the two killers for any FEOL-integrated ferroelectric. If those check out, this could simplify the gate stack roadmap for 2nm and beyond by removing an entire materials integration headache.

Key claim: ALD-grown TiO₂ exhibits stable ferroelectric switching at just 1nm thickness — two unit cells — on both silicon and amorphous carbon substrates at under 400 °C deposition temperature.

2. Intel 14A2 Goes Dual-Side Power Delivery — Backside Metallurgy Gets More Complex

What happened: Reports from ETNews and industry sources indicate Intel is developing a refined 14A2 (1.4nm-class) node that combines both front-side and back-side power delivery networks, moving beyond the PowerDirect/BSPDN approach in baseline 14A. (Sources: WCCFTech, Igor’sLAB)

Thin films take: Dual-side power delivery sounds like a packaging problem — and it is — but the real challenge lands on the deposition and CMP teams. You’re now looking at two separate metallization stacks: a front-side stack handling signal routing through the standard BEOL (probably 10–12 metal layers of Cu/low-k at these dimensions), and a back-side stack delivering power through the substrate using thick Cu or possibly Ru power rails. The back-side stack demands films that can survive the wafer flip, temporary bonding, and reveal etch without delaminating or suffering resistivity shift. That means every barrier layer — TaN, Co, whatever the liner of the week is — needs to hold up through a second thermal cycle that the front-side never had to endure. If you’re running the back-side PVD TiN liner at 400 °C and the front side has air-gap low-k dielectrics with a 350 °C ceiling, you’ve got a thermal budget collision that keeps process integration up at night. The BSPDN step alone adds roughly 15–20% more deposition passes to the total wafer flow. Anyone who’s had to babysit a Via-Middle TSV process knows that every extra back-side film stack multiplies the defectivity risk. Intel’s PowerVia was elegant because it was a single BSPDN solution. Going dual-sided means twice the interfacial engineering, twice the stress management, and twice the films that can peel.

Key claim: Dual-side power delivery on Intel 14A2 adds 15–20% more thin-film deposition passes and introduces thermal budget conflicts between back-side power rails and front-side low-k dielectrics.

3. Applied Materials Targets DRAM and Advanced Packaging with New Deposition & Etch Hardware

What happened: Applied Materials introduced new deposition and etch systems on June 15 designed for precision processing in increasingly deep and narrow 3D structures, specifically targeting DRAM capacitor scaling and advanced packaging applications. (Sources: Applied Materials, Insider Monkey)

Thin films take: Applied’s been quietly working the DRAM angle hard — their Endura Copper Barrier Seed IMS with Volta Ruthenium CVD has already been adopted by all leading logic makers for 3nm and beyond, and now they’re focusing that same toolset on DRAM. The DRAM capacitor is arguably the most demanding high-aspect-ratio structure in volume manufacturing: you’re looking at >60:1 AR with a ZrO₂/Al₂O₃/ZrO₂ (ZAZ) dielectric stack that needs sub-Å uniformity from top to bottom. Any new deposition hardware that can push that aspect ratio further while keeping leakage within spec is meaningful. On the advanced packaging side, the tools target hybrid bonding and 3D/3.5D interconnects. That means Cu-Cu direct bonding interfaces, which demand surfaces flat enough (sub-nm RMS roughness) that even a single 10Å particle kills the bond. The etch components likely address the scallop control and sidewall profile tuning needed for through-silicon vias at the packaging pitch — not the same regime as FEOL etching but equally unforgiving when your bonding pad is 2µm wide and needs a mirror finish. What I’ll be watching is whether their DRAM high-k ALD step change can extend the ZAZ stack to the 1c and 1d node generations, because DRAM makers are running out of dielectric headroom fast.

Key claim: Applied Materials’ new Deposition and Etch systems target the DRAM capacitor’s >60:1 aspect-ratio ZAZ stack and sub-nm Cu-Cu hybrid bonding surfaces for advanced packaging.