1. Glass Substrates Cross the Inflection Point — CoWoS Cost Surge Accelerates the Tectonic Shift
What happened: TrendForce published a landmark assessment on June 5 confirming that glass core substrates are targeting 2027 commercial launch and scaling toward mainstream adoption by 2030. The catalyst: CoWoS packaging costs have surged to $750–1,100 per chip, and hyperscaler demand for next-generation infrastructure is now the primary driver. Intel, SKC/Absolics, Samsung Electro-Mechanics, and the recently announced Intel-Odisha $3.3B India facility are all racing toward volume production.
Thin films take: This is the week the industry stopped asking “if” and started asking “when” for glass substrates, and if you’ve spent your career in PVD and wet-etch processes, you should be paying close attention — because everything changes when your substrate goes from organic laminate to borosilicate glass. The TrendForce report puts it plainly: silicon interposer yield losses on packages above 2,700mm² are driving CoWoS-L costs 20–40% higher than CoS, and glass substrates eliminate the interposer entirely. But from where I sit, the real thin-films story is the TGV (through-glass via) process. Standard reactive ion etch recipes that work beautifully on silicon dielectrics don’t transfer to glass — the etch chemistry, the sidewall angle control, the barrier seed layer adhesion — every deposition sequence in the packaging flow has to be revalidated for a glass substrate, and the dielectric build-up on glass defines defect density for the whole module. The Intel Odisha facility combined with the TrendForce timeline means we’ll see pilot-scale TGV PVD tool evaluations inside 18 months. If you’re a process integration engineer who hasn’t run a DOE on Ti/Cu seed adhesion to alkaline earth boroaluminosilicate glass yet, your calendar just got full.
Sources: TrendForce — Glass Substrates Eye 2027 Launch (Jun 5, 2026); SiliconAnalysts — CoWoS Packaging Cost: $750–1,100/Chip (Apr 2026); Intel Rio Rancho — Glass Substrate Mass Production Targets
2. TSMC Debuts A13/A12 Roadmap to 2029 — Deposition and Etch Engineers Get Their Next Decade of Work
What happened: At the 2026 North America Technology Symposium in Santa Clara (April 22–23), TSMC unveiled a roadmap extending through 2029 with A13 (1.3nm-class) and A12 (1.2nm-class) nodes. A13 promises 6% area reduction over A14, while A12 pushes further with continuous nanosheet architecture refinement and backside power delivery evolution. The roadmap also includes N2U (N2 with buried power rail), expanded CoWoS interposer sizes up to 9.5X reticle, and the SoW-X wafer-scale integration platform for next-gen AI training. A16 enters volume production in H2 2026 in Taiwan, with Arizona A16 production targeted for 2028.
Thin films take: Every TSMC roadmap refresh since A16 has leaned harder on backside power delivery, and A13/A12 are no exception. The Super Power Rail architecture — moving the power distribution network to the wafer backside — means we now need to deposit dielectric liners and Cu fill into via-middle structures that are etched from the back of a thinned wafer, with aspect ratios that push conventional PVD and CVD beyond their existing chamber hardware capabilities. A16 already requires >500 process steps per GAA transistor, and A13/A12 will add more — each angstrom-level shrink introduces additional spacer layers, workfunction metal tuning steps, and dielectric stack complexity that show up in every CVD and ALD chamber’s preventive maintenance schedule. The symposium also confirmed that TSMC does not believe high-NA EUV is required for A14, meaning the industry’s multi-patterning workload stays high — which is good news for anyone whose job security depends on running ASML NXE:3800E scanners at full utilization. And on the packaging side, the expanded CoWoS interposer roadmap (9.5X reticle by 2027) means the PVD seed layers and electroless Cu processes for those massive interposers become yield-limiting steps that demand chamber uniformity specs that today’s tools can barely hit across a 300mm wafer, let alone a reticle-scale interposer.
Sources: Cloud News — TSMC extends its lead until 2029 with A13, A12; New Electronics — TSMC Technology Symposium 2026; Insider Monkey; Tech-oracle.com
3. Samsung HBM5 Introduces Heat Path Block — A Packaging Thermal Challenge That Becomes a Thin-Films Problem
What happened: At COMPUTEX 2026 (June 2), Samsung unveiled the world’s first HBM5 mock-up, featuring a proprietary thermal management technology called Heat Path Block (HPB). HBM5 uses a 2nm base die (manufactured in-house at Samsung Foundry) and supports 12, 16, and 20-layer DRAM stacks. HPB adds dedicated thermal pillars that pull heat from inside the stacked dies — essentially a through-silicon via (TSV) architecture repurposed for thermal conduction rather than electrical interconnect. Volume production is projected around 2028, with Nvidia still uncommitted (SK Hynix remains the preferred HBM supplier).
Thin films take: Samsung’s HPB is a structure that exists entirely because the thin-films interfaces in HBM stacks can’t move heat fast enough. Here’s the physics: as HBM stacks go from 8 to 12 to 20 layers, the cumulative thermal resistance of the dielectric bonding layers — the SiO₂ or SiCN hybrid bond interfaces between each DRAM die — becomes the dominant heat transfer bottleneck. Every 10nm of dielectric between Cu hybrid bond pads adds measurable thermal impedance, and at 20 layers you’re looking at a total dielectric stack that can exceed 1µm of oxide between the hottest die and the package lid. HPB adds dedicated Cu thermal TSVs that bypass those dielectric interfaces entirely — but that means Samsung now needs to integrate thermal TSVs into the DRAM memory cell array processing flow, which they’ve never had to do before in HBM. The TSV etch for thermal vias is different from signal TSVs: lower aspect ratio but larger critical dimension, which changes the scalloping profile requirements on the Bosch etch process. And the dielectric liner deposition for thermal TSVs must balance electrical isolation (you don’t want Cu diffusion into DRAM cells) against thermal conductivity (too much liner and you’ve just recreated the problem you’re solving). For the process engineers at Samsung’s HBM line in Pyeongtaek, HPB means a whole new thin-films integration flow in the TSV module — and given that Samsung is already struggling to match SK Hynix’s HBM yields, adding a new thermal TSV process to the flow is a high-risk, high-reward bet.
Sources: Tom’s Hardware — Samsung shows first HBM5 mockup with HPB (Jun 2, 2026); TechTimes — HBM5 Debuts at Computex; Korea Times; Chosun Biz (Jun 2, 2026)
RELATED POSTS
View all
