Thin Films This Week — May 22, 2026

1. Intel 18A Yields Hit 7–8% Monthly Improvement; 14A ‘Holy Grail’ PDK 0.9 Due October 2026

What happened: Intel CEO Lip-Bu Tan announced 18A process yields are improving 7–8% per month—the industry standard cadence—and confirmed 14A PDK 0.9 is on track for October 2026, calling it “the Holy Grail” for external customers, while warning engineers they’ll be fired if chips exceed B0 stepping. (Wccftech)

Thin films take: I’ve been in process integration long enough to know that 7–8% monthly yield improvement on a debut GAA node is—if real—genuinely impressive. RibbonFET’s stacked nanosheets demand atomic-layer precision across a much larger effective gate perimeter than FinFET ever did. Every one of those horizontal channels needs conformal gate oxide, work-function metal, and high-k dielectric deposition that’s uniform top-to-bottom across the entire sheet stack. That’s an ALD challenge FinFET never posed. PowerVia adds another thin-films headache: backside metal deposition and planarization at a scale we’ve never done in production. The B0 stepping discipline matters because each mask respin on a GAA node costs months and millions. If Tan is serious about first-pass A0, he’s betting that his deposition and etch teams can deliver process windows tight enough—and stable enough—that the design-technology co-optimization doesn’t break between tapeout and first silicon. I’ll believe 14A risk production in 2028 when I see a fully qualified high-volume ALD process for sub-1.5nm-class gate dielectrics that doesn’t require three reworks per wafer lot.

2. EV Group to Demo Hybrid Bonding, IR LayerRelease at ECTC 2026—Enabling Sub-Micron 3D Stacking

What happened: EV Group (EVG) announced it will showcase its latest hybrid bonding (wafer-to-wafer and die-to-wafer), IR LayerRelease technology for nanometer-precision layer transfer through silicon, and maskless lithography at ECTC 2026, including a joint paper with Intel on high-speed bond overlay measurement. (EV Group)

Thin films take: This is the story that most directly affects what we do in the cleanroom every day. Hybrid bonding is fundamentally a thin films problem masquerading as a packaging problem. You’re asking two dielectric surfaces—typically SiOₒ deposited by PECVD or PVD—to fuse at low temperature with sub-micron alignment and zero voids across a 300 mm interface. The dielectric deposition uniformity, surface roughness, and plasma activation chemistry determine whether you get a bond that passes CMP or a rejected stack. EVG’s IR LayerRelease is particularly interesting: using an IR laser through silicon with inorganic release materials eliminates the glass carrier and its associated thermal budget constraints, which means you can transfer thinner device layers without warpage. For those of us who’ve spent years fighting carrier-glass CTE mismatch on 3D NAND and CMOS image sensor stacks, this is a genuinely useful trick. The Intel co-authored metrology paper matters too—bond overlay measurement at production speed has been the gating item for die-to-wafer hybrid bonding. If EVG’s overlay metrology breaks 100 nm at production throughput, that’s the unlock that makes chiplet stacking cost-effective at scale.

3. Samsung Strike Averted at 11th Hour—But Foundry Yield Concerns Remain

What happened: Samsung Electronics and its largest labor union reached a tentative wage deal just 90 minutes before a planned 18-day general strike by 48,000 workers was set to begin on May 21, with the deal now subject to a worker vote through May 28. (Korea JoongAng Daily)

Thin films take: From a process engineer’s perspective, the strike was a distraction from a deeper problem: Samsung’s SF2 (2nm GAA) yields are rumored to be stuck around 50–60%, versus TSMC’s N2 at 80%+. The labor situation matters because you can’t fix a yield problem if 48,000 people aren’t on the fab floor. But the real thin films issue here is that Samsung was first to GAA production with SF3E in 2022—three full years ahead of everyone else—and they still haven’t cracked the deposition uniformity challenge across their nanosheet stacks. GAA yields live or die on conformal ALD of high-k dielectrics and metal gate work-function layers inside those horizontal channels. If your ALD step coverage falls below 95% on the bottom-most sheet, you’re looking at threshold voltage shifts that kill die sort yields across the whole wafer. Samsung’s 2nm yields being stuck where TSMC’s were 18 months earlier suggests the gap isn’t just in patterning—it’s in deposition and etch precision at the atomic layer level. Until Samsung demonstrates a qualified high-volume ALD process for 2nm-class GAA that matches TSMC’s film uniformity, the foundry market stays a one-horse race regardless of labor peace.