Thin Films This Week — July 17, 2026

Three stories from the fab floor this week that matter for thin films and process engineering.

1. Intel Ships First High-Volume Logic Chips Using ASML High NA EUV on 18A

What happened: Intel became the first company to ship high-volume logic products using ASML’s High NA (0.55 NA) EUV lithography, with select Panther Lake layers on Intel 18A now dual-qualified across both NXE and EXE scanner platforms. Thin films take: This is the one I’ve been waiting for — not because of the optics, but because of what High NA does to the resist stack. At 0.55 NA, you’re pushing 8 nm half-pitch resolution, which means the photoresist thickness budget collapses. We’re now running sub-30 nm resist films on production wafers, and the etch selectivity problem becomes your new best friend and worst enemy. The dual-qualification is the sleeper here: same layer runs on either 0.33 NA or 0.55 NA, which means the hardmask stack — the SiON, the spin-on carbon, the anti-reflective layers — all had to be re-engineered to be scanner-agnostic. I’ve spent enough nights in the fab fighting reflectivity swings from a single-nm change in anti-reflective coating thickness to know how much work that took. The resist and underlayer film vendors just earned their keep this quarter.

2. TSMC and Samsung Hike Advanced Node Wafer Prices 5-15% as AI Demand Outpaces Capacity

What happened: TSMC raised wafer prices 5-10% across 3nm, 5nm, and 7nm nodes while Samsung selectively hiked 4nm, 5nm, and select 8nm automotive nodes by up to 15%, marking a structural shift from a buyer’s to a seller’s foundry market. Thin films take: Every time I see a wafer price hike headline, I think about the consumables budget. The deposition materials cost per wafer at 3nm has tripled versus 7nm — the ALD cycle count alone for the gate stack, the work-function metal layers, the multiple threshold-voltage Vt tuning films — it adds up fast. At 3nm, a single wafer goes through 80+ ALD cycles before you ever get to the first metallization step, and each cycle burns precursor that costs more per gram than silver. The price hikes aren’t just about EUV tool depreciation; they’re a direct reflection of film stack complexity. I’ve seen PVD targets for advanced nodes now cost 4x what they did at 28nm because the purity spec went from 5N to 6N5 and the grain size uniformity requirement tightened. Samsung’s selective pricing — only on 4nm and 5nm — tells me they’re still struggling with GAA film uniformity at SF2 yields, and they can’t justify a blanket hike until they solve the nanosheet epitaxial layer thickness control. That’s a deposition problem, plain and simple.

3. TSMC A14 (1.4nm) Progress Well Ahead of N2 at Same Stage, Record Quarterly Earnings

What happened: TSMC confirmed on its Q2 2026 earnings call that its A14 (1.4nm-class) process development has surpassed N2’s trajectory at the equivalent stage, with significant yield and performance improvements, and reported a record quarterly profit driven by insatiable AI chip demand. Thin films take: A14 going faster than N2 at the same stage is the kind of comment that either means you’ve solved your (1,0,0) vs (1,1,0) nanosheet orientation problem, or you haven’t and you’re talking around it. I’ll bet it’s the former. The film stack at 1.4nm requires gate-all-around with channel thickness control to within ±0.3 nm across a 300 mm wafer — that’s roughly two atomic layers of silicon — and the fact that TSMC is publicly claiming “significant yield improvements” on A14 means their SiGe epitaxial release layer etching and the subsequent channel release are landing within that window. For those of us in process integration, the really interesting part is how they’re managing the MOL (middle-of-line) contacts at this pitch. At 1.4nm, the contact CD is pushing below 12 nm, and you cannot get conformal TiN liner coverage with PVD anymore — you’re all-in on ALD TiN, and the resistivity penalty from the higher carbon content in the ALD-deposited film versus PVD is a constant tradeoff I don’t envy their integration team. Record earnings help pay for the 10,000 wafer experiments it’s going to take to dial that in.