Thin Films This Week — May 15, 2026

🍏 1. Apple Confirms Intel 18A-P Testing for iPhone, iPad, and Mac Chips — A Foundry Watershed

What happened: Multiple reports this week confirm Apple is actively testing Intel’s 18A-P process node at Fab 52 in Chandler, Arizona, with analyst Ming-Chi Kuo detailing small-scale 2026 testing, a 2027 ramp for M7-series chips, and potential 14A production for iPhone chips by 2028 — backed by a preliminary agreement reported by the Wall Street Journal on May 9.

Thin films take: I’ve been doing this long enough to remember when Intel was the unquestioned king of thin-film process control, back when everyone else was still trying to figure out hafnium-based high-k. The 18A process stack is no joke — RibbonFET GAA nanosheets with PowerVia backside power delivery means you’re depositing dielectric layers and metal fills on both sides of the wafer. That’s a fundamentally different challenge for every PECVD and PVD chamber in the line. The 18A-P variant reportedly optimizes for mobile power envelopes, which tells me they’ve tuned the interlayer dielectric (ILD) stack and contact resistance through specific ALD high-k/metal gate (HKMG) process changes. For those of us in process integration, the bigger story is what this means for deposition tool utilization at Intel’s Arizona fabs — AMAT Endura and Lam Kiyo chambers are going to be running triple shifts. The key question no one’s asking yet: how does PowerVia affect stress management in the thin-film stack? Backside processing completely changes the stress asymmetry budget.

Sources: MacRumors, WCCFTech, Engadget, Tom’s Hardware

📦 2. Samsung Display and LG Display Pivot to Glass Interposer Packaging — Display Thin-Film Expertise Goes Semiconductor

What happened: South Korea’s two largest display panel makers are actively reviewing entry into the advanced semiconductor packaging market, with Samsung Display and LG Display evaluating glass interposer opportunities as AI-driven demand for 2.5D and 3D packaging continues to outstrip supply through 2026, per market research firm Sigmaintell.

Thin films take: This one gets me genuinely excited, and here’s why — display fabs already run some of the most precise thin-film deposition and etch processes in any industry, just at much larger scales. A Gen 6 display substrate is 1500×1850mm; your standard 300mm wafer is a postage stamp by comparison. The crossover technology here is glass through-via (GTV) formation and metallization. If Samsung Display can adapt its existing PECVD and PVD tool sets to deposit barrier/seed layers for copper-filled through-glass vias at panel-level scale, they fundamentally change the cost structure of high-density interposers. LG Display has been working with Nippon Electric Glass on ultra-thin OLED substrates since 2025 — same core physics, different application. The real challenge isn’t deposition, it’s the via sidewall profile and conformality over a panel’s entire area. You need ALD-quality step coverage on a substrate that’s 20× the area of your standard wafer. That means tool redesign, not just recipe tweaks.

Sources: The Elec, Display Daily, TweakTown, DigiTimes

🔬 3. TSMC N2 (2nm) Poised for Production Ramp with Unprecedented Demand — First GAA Node for the Industry Leader

What happened: TSMC’s N2 process — its first Gate-All-Around (GAA) nanosheet technology — is set for H2 2026 mass production with 1.5× more tape-outs than N5 at the same stage, defect densities matching N3/N5 maturity, and plans for 60,000 wafers per month across four fabs including Fab 20 in Hsinchu and Fab 22 in Kaohsiung.

Thin films take: N2 is TSMC’s first departure from FinFET, and that means a completely new thin-film process integration playbook. The GAA nanosheet architecture requires multiple alternating layers of Si and SiGe epitaxy — you’re growing a superlattice of Si/SiGe, then selectively etching the SiGe sacrificial layers to release the nanosheets. That selective etch is one of the most demanding processes in the entire fab: you need atomic-scale etch selectivity between Si and SiGe while maintaining perfect nanosheet release across an entire 300mm wafer. From a deposition perspective, the gate stack changes significantly too — the wrap-around gate requires conformal ALD high-k (HfO₂-based) and metal gate (TiN/TaN work-function metals) deposition on all four sides of each nanosheet. That means your ALD cycle times increase substantially versus FinFET because every surface of the suspended channel needs coverage. TSMC claiming defect densities comparable to N5 at this stage is genuinely impressive — EOT (equivalent oxide thickness) control at the angstrom level across a 3D nanosheet stack is not trivial.

Sources: Tom’s Hardware, WCCFTech, New Electronics